1. Field of the Invention
The present invention relates to low-voltage high-speed frequency dividers and, more particularly, to a low-voltage high-speed frequency divider with reduced power consumption.
2. Description of the Related Art
A frequency divider is an electronic circuit that receives an input clock signal, and generates an output clock signal that has a frequency which is a fraction of the frequency of the input clock signal. One common type of frequency divider is a divide-by-two frequency divider, which divides down the frequency of the input clock signal by two. For example, a divide-by-two frequency divider generates a 12.5 GHz output clock signal in response to a 25 GHz input clock signal.
FIG. 1 shows a schematic diagram that illustrates an example of a conventional divide-by-two frequency divider 100. As shown in FIG. 1, frequency divider 100 includes a master latch 110 and a slave latch 112 that is connected to master latch 110. In the present example, master latch 110 and slave latch 112 are implemented as high-speed current-mode logic (CML) latches.
Master latch 110 and slave latch 112 each has a data input D, a clock input C, and an output Q, along with an inverted data input DZ, an inverted clock input CZ, and an inverted output QZ. The output Q and the inverted output QZ of master latch 110 are connected to the data input D and the inverted data input DZ of slave latch 112, respectively. However, the output Q of slave latch 112 is connected to the inverted data input DZ of master latch 110, and the inverted output QZ of slave latch 112 is connected to the data input D of master latch 110.
In addition, master latch 110 and slave latch 112 each has a pair of input transistors M1 and M2, a pair of clock transistors M3 and M4, and a pair of output transistors M5 and M6. Further, master latch 110 and slave latch 112 each has a resistor R1, a resistor R2, and a bias current source IS. All of the components are connected together in a conventional manner.
FIGS. 2A-2C show timing diagrams that illustrate the operation of frequency divider 100. FIG. 2A shows a full-rate clock signal CLK input to the clock input C, while FIG. 2B shows the output Q of master latch 110 and FIG. 2C shows the output Q of slave latch 112. As shown in FIGS. 2A-2C, both the output Q of master latch 110 and the output Q of slave latch 112 output a signal with a frequency that is one half the frequency of the clock signal CLK.
Although frequency divider 100 can operate at very high speeds, one of the drawbacks of frequency divider 100 is that the minimum supply voltage required by frequency divider 100 is relatively high. This is because the transistors in the master and slave latches 110 and 112 are vertically stacked three levels high.
As a result, the minimum supply voltage required by frequency divider 100 is the sum of the minimum voltage that must lie across the bias current sources IS, the minimum voltage that must lie across the clock transistors M3 and M4, and the minimum voltage that must lie across the input transistors M1 and M2.
One approach to reducing the minimum supply voltage required by a high-speed frequency divider is disclosed in U.S. Pat. No. 7,098,697 to Kucharski et al. The Kucharski frequency divider replaces the latch circuit utilized in master latch 110 and slave latch 112 with a latch circuit that has only two levels and, therefore, a lower minimum supply voltage requirement.
FIG. 3 shows a schematic diagram that illustrates an example of a conventional Kucharski divide-by-two frequency divider 300. As shown in FIG. 3, frequency divider 300 has a master latch 310 and a slave latch 312 that is connected to master latch 310 in the same manner that slave latch 112 is connected to master latch 110.
Master latch 310 and slave latch 312, however, each has a pair of input transistors Q1 and Q2, a first pair of clock transistors Q3 and Q4, a second pair of clock transistors Q6 and Q7, and a pair of storage transistors Q9 and Q10. Each latch 310 and 312 also has a bias current source ISW for the pair of clock transistors Q3 and Q4, a bias current source ISW for the pair of clock transistors Q6 and Q7, a bias current source IB for the pair of input transistors Q1 and Q2, and a bias current source IH for the pair of storage transistors Q9 and Q10.
In addition, each latch 310 and 312 has an output transistor Q5, a resistor R1, a resistor R3, and a diode D1 associated with the first pair of clock transistors Q3 and Q4. Further, each latch 310 and 312 has an output transistor Q8, a resistor R2, a resistor R4, and a diode D2 associated with the second pair of clock transistors Q6 and Q7.
Thus, as shown in FIG. 3, the transistors in the master and slave latches 310 and 312 are vertically stacked only two levels high. (The collectors of transistors Q1, Q2, Q4 and Q6 are connected to the supply voltage VDD by way of the resistors R1 and R2.) As a result, the minimum supply voltage required by frequency divider 300 is approximately the sum of the minimum voltage across the bias current source IB and the minimum voltage across the input transistors Q1 and Q2.
Although frequency divider 300 can operate with a low voltage at very high speeds, one of the drawbacks of frequency divider 300 is that frequency divider 300 consumes a significant amount of power. In addition, the clock signal input to frequency divider 300 must drive four transistors during each clock phase.
Thus, there is a need for a low-voltage high-speed frequency divider that consumes less power and drives less than four transistors during each clock phase.